A state machine typically converts a time series of input data through some function into a time series of output data appropriate for subsequent circuits. Typically, state machines include state elements, which store the current state of the machine and logic elements which produce the output and determine the next state as functions of the input and the current state.
A major and critical component in any synchronous state machine is the state element. Conventionally this element is in the form of a master-slave flip-flop. A conventional flip-flop circuit 10 is shown in FIG. 1 wherein a data line shown as conductor D is input into the D-port of a master latch 12. The Q output of master latch 12 is connected via conductor A to the D-port of a slave latch 14, the Q output of which forms the output of flip-flop 10.
A clock signal on conductor CK is inverted prior to input at the enable E-port of latch 12 and input directly into the E-port of latch 14. When the clock signal is low, master latch 12 tracks the D input, but the output is held constant by slave latch 14. On the positive clock edge, the output of master latch 12 is latched at the state of the D input and slave latch 14 passes this new state to the output, Q, causing a state transition. As used herein, an output is latched when held at the state existing on the input when the latch enters the latched mode. This is illustrated in the waveforms of FIG. 7 which relate to the conductors associated with latches 12 and 14 of flip-flop 10.
When the clock returns to a low state, the slave latch holds the current state on the output while the master latch tracks the D input to acquire the next "new state". It can be seen that no state transition occurs at the output on the negative clock edge. Thus, a full clock cycle is required for each output state transition. The clock frequency must therefore be twice that of the maximum frequency of any data line.
FIG. 2 illustrates a conventional flip-flop-based state machine 16. The state rate of this machine is equal to the clock frequency rate. Machine 16 includes a block of flip-flops 20 for storing the current state of the machine, and a logic block 18 which produces the state machine output and determines the next state, both as functions of the machine input and the current state. The Q outputs of flip-flop 20 are fed as inputs to the logic block 18, as are the state machine inputs D. The Z outputs of the logic block 18, which carry the next-state information, are coupled to the D inputs of the flip-flop 20. The Y outputs of logic block 18 serve as the state machine's output. The clocking signal is coupled to flip-flop 20 as shown.
It will be appreciated that this diagram is a generalized diagram in that flip-flop 20 may in fact be comprised of a plurality of flip-flops 10. Further, logic block 18 may be composed of a variety of logic elements which are necessary to provide the logic function for a desired application. Accordingly, several flip-flop outputs and several data connections between logic block 18 and flip-flops 20 may exist in this state machine. Also, some of the outputs of logic block 18 may be internally wired directly from inputs of logic block 18, when the logic functions desired for those outputs are equal to single inputs. Reference to the outputs of a logic block or means as being a function of the inputs includes, therefore, the direct connection of some outputs with inputs.
Flip-flop based state machines require a clock frequency at least two times the highest frequency of any state variable signal. Thus, the frequency limitations of the technology in use, and the high loading typical of clock distribution can cause very high speed logic designs to be limited first by poor clock fidelity.
Another factor often limiting state rates is the total data propagation delay time between state elements. The minimum state cycle time is the data propagation delay time through the logic block plus the data propagation delay time through the state element. (Data propagation delay time through a state element is defined to be the sum of the D to CK set-up time and the CK to Q delay time.) The delay for a flip-flop is roughly two times the propagation delay of each latch, since there are two serially connected latches.
The use of digital to analog converter bit-cell structures incorporating parallel-connected latches clocked at a reduced frequency is used to prevent glitches in the converter output. For instance, see HSIEH et al., "A 12-Bit One-Gword/S GaAs Digital-to-Analog Convertor System", IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 6, December 1987, pages 1048-1054. However, such an arrangement has not been used as a state element in a state machine heretofore. Further, a state element design having a propagation delay of only a single latch has not heretofore been provided.